138 lines
3.7 KiB
Verilog
138 lines
3.7 KiB
Verilog
`timescale 1ns/1ps
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module tb_data_assemble();
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// 参数定义
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parameter PIXEL_WIDTH = 8;
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parameter GRAY_PIXEL_CNT = 32;
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parameter RGB_PIXEL_CNT = 8;
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// 信号定义
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reg clk;
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reg rst_n;
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reg en;
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reg input_pixel_type;
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reg [PIXEL_WIDTH-1:0] ir_ch0;
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reg [PIXEL_WIDTH-1:0] ir_ch1;
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reg [PIXEL_WIDTH-1:0] ir_ch2;
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reg pixel_valid;
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wire done;
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wire [255:0] assembled_data;
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// 生成时钟（100MHz）
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initial begin
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clk = 1'b0;
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forever #5 clk = ~clk;
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end
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// 实例化DUT
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data_assemble #(
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.PIXEL_WIDTH (PIXEL_WIDTH),
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.GRAY_PIXEL_CNT (GRAY_PIXEL_CNT),
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.RGB_PIXEL_CNT (RGB_PIXEL_CNT)
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) u_data_assemble (
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.clk (clk),
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.rst_n (rst_n),
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.en (en),
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.input_pixel_type(input_pixel_type),
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.ir_ch0 (ir_ch0),
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.ir_ch1 (ir_ch1),
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.ir_ch2 (ir_ch2),
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.pixel_valid (pixel_valid),
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.done (done),
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.assembled_data (assembled_data)
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);
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// 生成FSDB波形
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initial begin
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$fsdbDumpfile("tb.fsdb");
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$fsdbDumpvars(0, tb_data_assemble);
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$fsdbDumpMDA(0, tb_data_assemble);
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end
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// 测试场景
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initial begin
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// 初始化
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rst_n = 1'b0;
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en = 1'b0;
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input_pixel_type = 1'b0;
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ir_ch0 = 8'd0;
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ir_ch1 = 8'd0;
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ir_ch2 = 8'd0;
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pixel_valid = 1'b0;
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// 释放复位
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#20;
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rst_n = 1'b1;
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#20;
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// -------------------------- 测试1：Gray模式拼接 --------------------------
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$display("[%0t] Test 1: Gray mode assembly", $time);
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input_pixel_type = 1'b0;
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en = 1'b1;
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#10;
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// 输入32个数据（0x01~0x20）
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repeat (GRAY_PIXEL_CNT) begin
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@(posedge clk);
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pixel_valid = 1'b1;
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ir_ch0 = ir_ch0 + 8'd1; // 最后一个数据为0x20
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end
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@(posedge clk);
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pixel_valid = 1'b0;
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wait(done == 1'b1);
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#10;
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// 验证首8bit（0x01）和尾8bit（0x20）
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$display("[%0t] Gray first 8bit: 0x%0h (Expected: 0x1)",
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$time, assembled_data[255:248]);
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$display("[%0t] Gray last 8bit: 0x%0h (Expected: 0x20)",
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$time, assembled_data[7:0]);
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#20;
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// -------------------------- 测试2：RGB模式拼接 --------------------------
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$display("[%0t] Test 2: RGB mode assembly", $time);
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input_pixel_type = 1'b1;
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ir_ch0 = 8'd0;
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ir_ch1 = 8'd0;
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ir_ch2 = 8'd0;
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#10;
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// 输入8组数据：CH0=10*N, CH1=20*N, CH2=30*N（N=1~8）
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repeat (RGB_PIXEL_CNT) begin
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@(posedge clk);
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pixel_valid = 1'b1;
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ir_ch0 = ir_ch0 + 8'd10; // 10,20,...,80（0x0a,0x14,...,0x50）
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ir_ch1 = ir_ch1 + 8'd20; // 20,40,...,160（0x14,0x28,...,0xa0）
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ir_ch2 = ir_ch2 + 8'd30; // 30,60,...,240（0x1e,0x3c,...,0xf0）
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end
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@(posedge clk);
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pixel_valid = 1'b0;
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wait(done == 1'b1);
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#10;
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// 验证首32bit（{8'd0,30,20,10}=0x00_1e_14_0a）和尾32bit（{8'd0,240,160,80}=0x00_f0_a0_50）
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$display("[%0t] RGB first 32bit: 0x%08h (Expected: 0x001e140a)",
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$time, assembled_data[255:224]);
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$display("[%0t] RGB last 32bit: 0x%08h (Expected: 0x00f0a050)",
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$time, assembled_data[31:0]);
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#20;
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// -------------------------- 测试3：关闭使能 --------------------------
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$display("[%0t] Test 3: Disable assembly", $time);
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en = 1'b0;
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input_pixel_type = 1'b0;
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@(posedge clk);
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pixel_valid = 1'b1;
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ir_ch0 = 8'd1;
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@(posedge clk);
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pixel_valid = 1'b0;
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#10;
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$display("[%0t] Disable check: done=%b (Expected:0)", $time, done);
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#20;
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$display("[%0t] All tests completed!", $time);
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$finish;
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end
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endmodule |